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AES is implemented by using VHDL

The algorithm consists of four stages that make up a round which is iterated 10 times for a 128-bit length key, 12 times for a 192-bit key, and 14 times for a 256-bit key. The first stage "SubBytes" transformation is a non-linear byte substitution for each byte of the block. The second stage "ShiftRows" transformation cyclically shifts (permutes) the bytes within the block. The third stage "MixColumns" transformation groups 4-bytes together forming 4-term polynomials and multiplies the polynomials with a fixed polynomial mod (x^4+1). The fourth stage "AddRoundKey" transformation adds the round key with the block of data.

The hardware implementation of AES could provide either high performance or low cost for specific applications. At backbone communication channels, or at heavily loaded server, it is not possible to lose processing speed running cryptography algorithms in general software, which drops the efficiency of the overall system. On the other side, a low cost and small design can be used in smart card applications, allowing a wide range of equipment to operate securely.

The design goal of this project is to create a demonstration of the AES-128 for the end user and not for integration into a communication or data storage device; however this design could be modified to such ends. The main objective of the project is to produce an optimized VHDL code for performance purpose, capable of achieving better performance than common software implementation.

The proposed project AES is implemented by using VHDL. The device is operated at 100.29 MHz when targeted to Spartan 3E.