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INTELLIGENT BATTERY CHARGING

INTELLIGENT BATTERY CHARGING USING PIC16F73 MICRO CONTROLLER FOR MISSILE TEST EQUIPMENT.

It is designed and developed based on microprocessor technology for Konkurs Missile Test Equipment (KMTE) assembled on a PCB module mounted on a bracket, in turn to be fitted on front panel PCB frame of test equipment.

Charger is intended to charge Ni-Cd/Ni-Al battery pack capacity of 1.8AH/2.2AH respectively. It shall operate on AC mains power of 230V AC at 50Hz with specified variation. The regulated power supply of charger works on SMPS and converts incoming AC voltages to DC(maximum 60V) for charging the battery. Charging is done in two modes. Normal mode and boost mode. At the end of normal/boost charge, the charges automatically charge over to the trickle mode. Mode of changing is switch selectable and the charging mode can be indicated LEDs which are connected on D-type connector.

The charge is based on a PIC16F73 micro controller. The micro controller provides desired features of time tracking, detection of negative voltage shift to monitor the charging process. The input AC voltage is passed through the input fuse and line filter, followed by bridge rectifier. The resultant DC voltage is fed to the transformer with the separate taps for charger circuit and micro controller circuit. Output of the charge is maintained at nominal voltage of 60V DC. Required sense lines and control lines are provided between the charger circuit and microprocessor circuit. The status of charging is detected using micro controller provision is available for selection of normal boost charge. LED can be connected to the connector for charge indicator. Selection provision shall also be made for selection in battery type.

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AES is implemented by using VHDL

The algorithm consists of four stages that make up a round which is iterated 10 times for a 128-bit length key, 12 times for a 192-bit key, and 14 times for a 256-bit key. The first stage "SubBytes" transformation is a non-linear byte substitution for each byte of the block. The second stage "ShiftRows" transformation cyclically shifts (permutes) the bytes within the block. The third stage "MixColumns" transformation groups 4-bytes together forming 4-term polynomials and multiplies the polynomials with a fixed polynomial mod (x^4+1). The fourth stage "AddRoundKey" transformation adds the round key with the block of data.

The hardware implementation of AES could provide either high performance or low cost for specific applications. At backbone communication channels, or at heavily loaded server, it is not possible to lose processing speed running cryptography algorithms in general software, which drops the efficiency of the overall system. On the other side, a low cost and small design can be used in smart card applications, allowing a wide range of equipment to operate securely.

The design goal of this project is to create a demonstration of the AES-128 for the end user and not for integration into a communication or data storage device; however this design could be modified to such ends. The main objective of the project is to produce an optimized VHDL code for performance purpose, capable of achieving better performance than common software implementation.

The proposed project AES is implemented by using VHDL. The device is operated at 100.29 MHz when targeted to Spartan 3E.

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COMPLEX PROGRAMMABLE LOGIC DEVICE

As chip densities increased, it was natural for the PLD manufacturers to evolve their products into larger (logically, but not necessarily physically) parts called Complex Programmable Logic Devices (CPLDs). For most practical purposes, CPLDs can be thought of as multiple PLDs (plus some programmable interconnect) in a single chip. The larger size of a CPLD allows we to implement either more logic equations or a more complicated design. In fact, these chips are large enough to replace dozens of the pesky parts.

Because CPLDs can hold larger designs than PLDs, their potential uses are more varied. They are still sometimes used for simple applications like address decoding, but more often contain high-performance control-logic or complex finite state machines. At the high-end (in terms of numbers of gates), there is also a lot of overlap in potential applications with FPGAs. Traditionally, CPLDs have been chosen over FPGAs whenever high-performance logic is required. Because of its less flexible internal architecture, the delay through a CPLD (measured in nanoseconds) is more predictable and usually shorter.

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Design and Implementation of RC4 stream for WI-FI

In Cryptography the main feature is to work out with problems, which associated with secrecy, authentication and integrity. In order to handle all the cryptographic problems many kinds of cryptographic algorithms have been invented. The complexity of these problems made several categories of cryptographic algorithms. A much known is the RC4 stream cipher. The project deals with the design of RC4 stream cipher for wireless LAN security.

The 802.11 is a wire LAN, uses a collision avoidance (CSMA/CA) mechanism together with a positive acknowledges scheme and critical carrier sense as well as physical carrier sense methods. The important part of wireless MAC layer design is the security (WEP/RC4 algorithm) implementation. The security protocol is the part of the data link layer. This protocol uses RC4 cryptographic algorithm and its intention is to prevent attempts of thefts and invasions. RC4 is the most widely-used software stream cipher and is used in popular protocols such as Secure Sockets Layer (SSL) (to protect Internet traffic) and WEP (to secure wireless networks) and is remarkable for its simplicity and speed in software.

RC4 uses a variable key from 1 to 256 bytes to initialize a 256-byte array. the array is used for subsequent generation of pseudo-random bytes and then generates a pseudorandom stream, which is XORed with the plaintext/cipher text to give the cipher text/plain text. The RC4 stream cipher works in two phases the key setup phase and the pseudorandom key stream generator phase. Both phases must be performed for every new key. The primary functions are generation of 256-bytes key data from variable key length (6to16bytes), initialization of the key setup, swapping of 256-bytes between two blocks of 256 bytes (to randomize the bytes). Control and storage blocks design and implementation and key stream cipher bytes generation.

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Symfony

Symfony is a web application framework for PHP5 projects.It aims to speed up the creation and maintenance of web applications, and to replace the repetitive coding tasks by power, control and pleasure.

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XPCOM

similar to (Cross Platform Component Object Model) is a cross platform component modelCORBA or Microsoft COM. It has multiple language bindings and IDL descriptions so programmers can plug their custom functionality into the framework and connect it with other components.

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