EXPERT'S EDGE TEAM WISHES YOU MARRY CHRISTMAS
Thursday, December 24, 2009
Wednesday, December 23, 2009
VERY SOON WE PROVIDES...................... ...................................contd............MESSEGE
Expert's edge ideas are compiled by experts in the engineering(all branches) . Every day our team are being added lots of latest seminars and projects topics into our list. A educationalist team is working to find out the latest topics(projects, seminar),Which is useful for the students. We posted the projects and seminar topics every day so that stay with us.
Tuesday, December 22, 2009
latest project topics
BUS STOP NAME INDICATION SYSTEM
If the passenger has some residual vision, they may see outlines of useful landmarks that indicate the approach to their bus stop. The near or totally blind rely on identifying directional changes that the bus makes to find their bus stop. Seeking confirmation from a fellow passenger or from the driver is another alternative although it does require a lot of confidence to do this.
Keeping in mind these problems, this system has been planned to facilitate a blind person or a person new to the area who doesn’t have knowledge on bus stop information.
This system has a transmitter at every bus stop which continuously transmitting a unique ID .Bus contains a main unit which receives transmitted ID and indicates the passengers the arrived stop.
Transmitter unit comprises of a Microcontroller (AT89c51) unit which generates a unique bus stop ID for every bus stop and multiple transmitter units. IRED to transmit the code. Receiver unit comprises of IR receiver (TSOP1738) to detect and demodulate the transmitted code which is detected by the microcontroller and indication is produced.
Keeping in mind these problems, this system has been planned to facilitate a blind person or a person new to the area who doesn’t have knowledge on bus stop information.
This system has a transmitter at every bus stop which continuously transmitting a unique ID .Bus contains a main unit which receives transmitted ID and indicates the passengers the arrived stop.
Transmitter unit comprises of a Microcontroller (AT89c51) unit which generates a unique bus stop ID for every bus stop and multiple transmitter units. IRED to transmit the code. Receiver unit comprises of IR receiver (TSOP1738) to detect and demodulate the transmitted code which is detected by the microcontroller and indication is produced.
latest project topics
PC Based data acquisition system
PC Based data acquisition system by stimulating SPI and I2C protocol
Many times it is required to monitor physical phenomena such as temperature, pressure humidity, light intensity, sound intensity, force, etc. Such physical phenomena can be monitored by digital systems employing sensors. However sensor generally produces a change in the resistance, voltage or current. All such phenomena can be converted in to a change in voltage levels. Since the sensors and the subsequent signal conditioning circuits provide a proportionate change in voltage with respective the phenomena, this cannot be directly interpreted by a digital system. A sensor is ussaually an analog voltage and can take any value between +10 to -10 volts. However a digital system has only two states (ON) or (OFF). Thus it is required to have additional circuitry between the digital systems and analog systems that translate the analog signals in to a digital signals. Such conversion can be perform by an analog to digital converter.
The Serial Peripheral interface Bus or SPI (often pronounced “spy”) bus Is a synchronous serial data link standard that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. The I2C bus physically consists of two active wires and a ground connection. The active wires called SDA and SCL, are both bi-directional. SDA is a serial data line, SCL is a serial clock line.
contd....
Many times it is required to monitor physical phenomena such as temperature, pressure humidity, light intensity, sound intensity, force, etc. Such physical phenomena can be monitored by digital systems employing sensors. However sensor generally produces a change in the resistance, voltage or current. All such phenomena can be converted in to a change in voltage levels. Since the sensors and the subsequent signal conditioning circuits provide a proportionate change in voltage with respective the phenomena, this cannot be directly interpreted by a digital system. A sensor is ussaually an analog voltage and can take any value between +10 to -10 volts. However a digital system has only two states (ON) or (OFF). Thus it is required to have additional circuitry between the digital systems and analog systems that translate the analog signals in to a digital signals. Such conversion can be perform by an analog to digital converter.
The Serial Peripheral interface Bus or SPI (often pronounced “spy”) bus Is a synchronous serial data link standard that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. The I2C bus physically consists of two active wires and a ground connection. The active wires called SDA and SCL, are both bi-directional. SDA is a serial data line, SCL is a serial clock line.
contd....
latest project topics
On power ON, the AC current passes through the fuse and the filter, this filter out any noise or spikes. After the filter passes through the rectifier which converts AC to DC. Next to rectifier it passes through the transformer and provides a constant voltage to the charger. Past of the winding from transformer is taken TOP switch to generate supply. The micro controller reads the input current voltage input coming from the batter and Vref generated in the circuit. The controller generates the current reference voltage to current loop circuit by reading the inputs and adjusting the PWM in the controller according to the inputs taken.
The project involves both hardware and software. The primary component used in the project i.e., PIC16F73 Microcontroller. has to be studied and tested. The other components are available in discrete. These components are to be assembled on the PCB board and then proper connections are to be made. Coded microcontroller i.e., PIC16F73 has to be used in order to perform the charging operation by connecting the PCB module to the system using RS-232 cable.
The project involves both hardware and software. The primary component used in the project i.e., PIC16F73 Microcontroller. has to be studied and tested. The other components are available in discrete. These components are to be assembled on the PCB board and then proper connections are to be made. Coded microcontroller i.e., PIC16F73 has to be used in order to perform the charging operation by connecting the PCB module to the system using RS-232 cable.
latest project topics
ASYNCHRONOUS FIFO FOR EMBEDDED APPLICATIONS
DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS FIFO FOR EMBEDDED APPLICATIONS
A FIFO is used as a "First In-First Out" memory buffer between two asynchronous systems with simultaneous write and read access to and from the FIFO, these accesses being independent of one another. Data written into a FIFO is sequentially read out in a pipelined manner, such that the first data written into a FIFO will be the first data read out of the FIFO.
FIFO status flag outputs are a function of the comparison of the respective write and read pointers. A FIFO will always have some status flag outputs; at least a flag that indicates the empty condition and a flag that indicates the full condition.
An asynchronous FIFO refers to a FIFO design where data values are written to a FIFO buffer from one clock domain and the data values are read from the same FIFO buffer from another clock domain, where the two clock domains are asynchronous to each other.
Attempting to synchronize multiple changing signals from one clock domain into a new clock domain and insuring that all changing signals are synchronized to the same clock cycle in the new clock domain has been shown to be challenging. FIFOs are used in designs to safely pass multi-bit data words from one clock domain to another. Data words are placed into a FIFO buffer memory array by control signals in one clock domain, and the data words are removed from another port of the same FIFO buffer memory array by control signals from a second clock domain. Conceptually, the task of designing a FIFO with these assumptions seems to be easy. The difficulty associated with doing FIFO design is related to generating the FIFO pointers and finding a reliable way to determine full and empty status on the FIFO.
In this project, an asynchronous FIFO is designed to pass data between different clock domains using Gray code pointers that are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions.
A FIFO is used as a "First In-First Out" memory buffer between two asynchronous systems with simultaneous write and read access to and from the FIFO, these accesses being independent of one another. Data written into a FIFO is sequentially read out in a pipelined manner, such that the first data written into a FIFO will be the first data read out of the FIFO.
FIFO status flag outputs are a function of the comparison of the respective write and read pointers. A FIFO will always have some status flag outputs; at least a flag that indicates the empty condition and a flag that indicates the full condition.
An asynchronous FIFO refers to a FIFO design where data values are written to a FIFO buffer from one clock domain and the data values are read from the same FIFO buffer from another clock domain, where the two clock domains are asynchronous to each other.
Attempting to synchronize multiple changing signals from one clock domain into a new clock domain and insuring that all changing signals are synchronized to the same clock cycle in the new clock domain has been shown to be challenging. FIFOs are used in designs to safely pass multi-bit data words from one clock domain to another. Data words are placed into a FIFO buffer memory array by control signals in one clock domain, and the data words are removed from another port of the same FIFO buffer memory array by control signals from a second clock domain. Conceptually, the task of designing a FIFO with these assumptions seems to be easy. The difficulty associated with doing FIFO design is related to generating the FIFO pointers and finding a reliable way to determine full and empty status on the FIFO.
In this project, an asynchronous FIFO is designed to pass data between different clock domains using Gray code pointers that are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions.
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